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KS0107B
64CH COMMON DRIVER FOR DOT MATRIX LCD
INTRODUCTION
100 QFP-1420C The KS0107B is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the KS0108B ( 64 channel segment driver). The KS0107B is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the KS0108B (64 channel segment driver).
FEATURES
* Dot matrix LCD common driver with 64 channel output * 64-bit shift register at internal LCD driver circuit * Internal timing generator circuit for dynamic display * Selection of master/slave mode * Applicable LCD duty : 1/48, 1/64, 1/96, 1/128 * Power supply voltage: + 5V 10% * LCD driving voltage : 8V~17V (VDD-VEE) * Interface Driver COMMON Other KS0107B SEGMENT KS0108B MPU Controller
100 TQFP-1414
* High voltage CMOS process * 100QFP / 100TQFP and bare chip available
1/20
KS0107B
64CH COMMON DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
C1 C2 C3
C62 C63 C64
V0L V1L V4L V5L
64-bit LCD driver
V0R V1R V4R V5R
64-bit bi-directional shift register
DIO1 PCLK2 SHL
Data shift direction & Phase selection control circuit
DIO2
M CL2 C R CR Timing generator circuit FRM CLK1 CLK2
OSC
VDD
VSS
VEE
DS1
DS2
MS
FS
Fig 1. KS0107B Functional block diagram
2/20
KS0107B PIN CONFIGURATION 1. 100QFP
C23 100 C24 99 C25 98 C26 97 C27 96 C28 95 C29 94 C30 93 C31 92 C32 91
64CH COMMON DRIVER FOR DOT MATRIX LCD
C33 90
C34 89
C35 88
C36 87
C37 86
C38 85
C39 84
C40 83
C41 82
C42 81 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 61 C62 C63 C64 VEE V1R V4R V5R V0R NC CL2 NC
C22 C21 C20 C19 C18 C17 C16 C15 C14
1 2 3 4 5 6 7 8 9
80 79 78 77 76 75 74 73 72 71 70 69
C13 10 C12 11 C11 12
KS0107B
C10 13 C9 14 C8 15
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C7 16 C6 17
C5 18 C4 19 C3 C2 C1 VEE 20 21 22 23
V1L 24 V4L 25
V5L 26 V0L 27
VDD 28 DIO1 FS 29 30
40
42
38
39
43
44
45
46
47
48
49
50
31 DS1
32 DS2
33 C
34 NC
35 R
36 NC
37 CR
41
NC
PCLK2
DIO2
SHL
VSS
NC
MS
FRM
M
Fig2. 100 QFP Top View
NC
3/20
CLK2
CLK1
NC
KS0107B PAD DIAGRAM ( Chip layout for the 100QFP )
64CH COMMON DRIVER FOR DOT MATRIX LCD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
100 99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80 79 78 77 76 75 74 73 72
KS0107B
71 70 69 68
Y ( 0, 0 ) X
67 66 65 64 63 62
CHIP PAD
SIZE
:
3450 x 4000
61 60 59 58 57 56 55 54
SIZE UNIT
: 100 x 100 : m
28
29
30
31
32
33
35
37
39
40
42
43
44
46
47
49
50
52
* There is the mark KS0107B on the center of the chip
4/20
KS0107B PAD LOCATION (100QFP)
PAD NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 PAD NAME C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS DS1 DS2 C R COORDINATE X -1314.5 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1345.6 -1127.6 -979.6 -827.6 -677.6 -527.6 -377.6 Y 1775.4 1630 1505 1380 1255 1130 1005 880 775 630 505 380 255 130 5 -120 -245 -370 -495 -620 -745 -870 -995 -1120 -1245 -1370 -1495 -1775 -1775 -1775 -1775 -1775 -1775 -1775 PAD NUMBER 37 39 40 42 43 44 46 47 49 50 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 PAD NAME CR SHL VSS MS CLK2 CLK1 FRM M PCLK2 DIO2 CL2 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47
64CH COMMON DRIVER FOR DOT MATRIX LCD
UNIT (m)
COORDINATE X -227.6 -77.6 113.8 308.7 458.7 608.7 758.7 908.7 1058.7 1208.7 1358.7 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 Y -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1495 -1370 -1245 -1120 -995 -870 -745 -620 -495 -370 -245 -120 5 130 255 380 505 630 755 880 1005 1130 1255 PAD NUMBER 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PAD NAME C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 COORDINATE X 1500.9 1500.9 1500.9 1310.5 1185.5 1060.5 935.5 810.5 685.5 560.5 435.5 310.5 185.5 60.5 -64.5 -189.5 -314.5 -439.5 -564.5 -689.5 -814.5 -939.5 -1064.5 -1189.5 Y 1380 1505 1630 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4
5/20
KS0107B 2. 100TQFP
64CH COMMON DRIVER FOR DOT MATRIX LCD
V1R
V4R
V5R
V0R
C47
C48
C51
C53
C54
C55
C56
C57
C58
C60
C61
C62
C63
C64
C45 75
C46 74
C49
C50
C52
C59
VEE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
73
72
71
70
69
68
67
66
65
C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20
76 77 78 79 80
50 49 48 47 46
NC CL2 NC DIO2 PCLK2 NC M FRM NC CLK1 CLK2 MS NC Vss SHL NC CR NC R NC C DS2
81 45 82 44 83 43 84 42 85 41 86 40 87 88 89 90 36 91 92 34 93 94 95 96 97 98 99 100 33 32 31 30 29 35 39
KS0107B
38 37
28 DS1 27 FS 26 DI01
17
18
19
10
11
12
13
15
20
21
22
23
24
25
14
16
1 C19
2 C18
3 C17
4 C16
5 C15
6 C14
Fig3.
7 C13
8 C12
9 C11
C8
100 TQFP Top View
C10
C9
C7
C4
C3
C2
C1
V4L
V5L
V0L
C6
6/20
C5
V1L
VDD
VEE
KS0107B PAD DIAGRAM (Chip layout for the 100TQFP)
64CH COMMON DRIVER FOR DOT MATRIX LCD
100 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81 80
79
78
77
76 75 74 73 72 71 70 69 68
KS0107BTQ
67 66 65 64
Y
63 62 61
X ( 0, 0 )
60 59 58
CHIP SIZE PAD SIZE UNIT
: 3850 x 4100 : 100 x 100 : m
57 56 55 54 53 52 51
26
27
28
29
30
32
34
36
37
39
40
41
43
44
46
47
49
* There is the mark KS0107BTQ on the center of the chip.
7/20
KS0107B PAD LOCATION (100TQFP)
64CH COMMON DRIVER FOR DOT MATRIX LCD
UNIT (m)
PAD NUM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
PAD NAME C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS DS1 DS2 C R CR SHL VSS MS CLK2 CLK1 FRM M PCLK2
COORDINATE X Y -1697 1534 -1697 1409 -1697 1284 -1697 1159 -1697 1034 -1697 909 -1697 784 -1697 659 -1697 534 -1697 409 -1697 284 -1697 159 -1697 34 -1697 -91 -1697 -216 -1697 -341 -1697 -466 -1697 -591 -1697 -716 -1697 -841 -1697 -966 -1697 -1091 -1697 -1216 -1697 -1341 -1697 -1466 -1245 -1821 -1095 -1821 -945 -1821 -795 -1821 -645 -1821 NC -495 -1821 NC -345 -1821 NC -195 -1821 0 -1821 NC 195 -1821 345 -1821 495 -1821 NC 645 -1821 795 -1821 NC 945 -1821
PAD NUM 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
PAD NAME DIO2 CL2 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28
COORDINATE X Y 1095 -1821 NC 1245 -1821 NC 1697 -1466 1697 -1341 1697 -1216 1697 -1091 1697 -966 1697 -841 1697 -716 1697 -591 1697 -466 1697 -341 1697 -216 1697 -91 1697 34 1697 159 1697 284 1697 409 1697 534 1697 659 1697 784 1697 909 1697 1034 1697 1159 1697 1284 1697 1409 1697 1534 1500 1822 1375 1822 1250 1822 1125 1822 1000 1822 875 1822 750 1822 625 1822 500 1822 375 1822 250 1822 125 1822 0 1822 -125 1822 -250 1822 -375 1822 -500 1822
PAD NUM 93 94 95 96 97 98 99 100
PAD NAME C27 C26 C25 C24 C23 C22 C21 C20
COORDINATE X Y -625 1822 -750 1822 -875 1822 -1000 1822 -1125 1822 -1250 1822 -1375 1822 -1500 1822
8/20
KS0107B PIN DESCRIPTION
PIN NUM QFP(TQFP) 28(25) 40(37) 23(20),58(55) 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) SYMBOL VDD VSS VEE V0L, V0R V1L, V1R V4L, V4R V5L, V5R INPUT/OUTPUT Power
64CH COMMON DRIVER FOR DOT MATRIX LCD
DESCRIPTION For internal logic circuit (+5V 10%) GND ( = 0 V) For LCD driver circuit Bias supply voltage terminals to drive LCD. Select Level V0L(R), V5L(R) Non-Select Level V1L(R), V4L(R)
Power
42(39)
MS
Input
39(36)
SHL
Input
V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should be connected by the same voltage. Selection of master/slave mode i) Master mode (MS=1) DIO1, DIO2, CL2 and M is output state. ii) Slave mode (MS=0) SHL=1DIO1 is input state (DIO2 is output state) SHL=0DIO2 is input state (DIO1 is output state) CL2 and M are input state. Selection of data shift direction. SHL H L Data shift direction DIO1C1 ...... C64DIO2 DIO2C64 ...... C1DIO1
49(46)
PCLK2
Input
Selection of shift clock (CL2) phase. PCLK2 H L Shift clock (CL2) phase data shift at the rising edge of CL2 data shift at the falling edge of CL2
30(27)
FS
Input
31(28) 32(29)
DS1 DS2
Input
Selection of oscillation frequency. i) Master mode When the frame frequency is 70 Hz, the oscillation frequency should be fosc=430 kHz at FS=1 (VDD) fosc=215 kHz at FS=0 (VSS) ii) Slave mode Connect to VDD. Selection of display duty. i) Master mode DS1 L L H H ii) Slave mode Connect to VDD. DS2 L H L H Duty 1/48 1/64 1/96 1/128
9/20
KS0107B PIN DESCRIPTION (continued)
PIN NUM QFP(TQFP) 33(30) 35(32) 37(34) SYMBOL INPUT/OUTPUT
64CH COMMON DRIVER FOR DOT MATRIX LCD
DESCRIPTION RC Oscillator i) Master mode : use these terminals as shown below.
KS0107B R Rf CR Cf open external clock open C R KS0107B CR C
C R CR
ii) Slave mode : stop the oscillator as shown below.
KS0107B R CR C
open
VDD
open
44(41), 43(40)
CLK1 CLK2 FRM
Output
46(43)
Output
47(44)
M
Input / Output
52(49)
CL2
Input / Output
29(26) 50(47)
DIO1 DIO2
Input / Output
Operating clock output for the KS0108B i) Master mode : connection to CLK1 and CLK2 of the KS0108B ii) Slave mode : open Synchronous frame signal. I) Master mode : connection to FRM of the KS0108B ii) Slave mode : open Alternating signal input for LCD driving. i) Master mode : output state Connection to M of the KS0108B ii) Slave mode : input state Connection to the controller Data shift clock I) Master mode : output state Connection to CL of the KS0108B ii) Slave mode : input state Connection to shift clock terminal of the controller. Data input/output pin of internal shift register. MS H L SHL H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input
22~1 (19~1) 100~59 (100~56)
Common signal output for LCD driving. C1~C64 Output DATA L L H H M L H L H OUT V1 V4 V5 V0
34(31),36(33) 38(35),41(38) 45(42),48(45) 51(48),53(50)
NC
No Connection
10/20
KS0107B MAXIMUM ABSOLUTE LIMIT
Characteristic
Operating Voltage Supply Voltage Driver Supply Voltage Operating Temperature Storage Temperature
64CH COMMON DRIVER FOR DOT MATRIX LCD
Symbol
VDD VEE VB VLCD T OPR T STG
Value
-0.3~+7.0 VDD-19.0~VDD+0.3 -0.3~VDD+0.3 VEE-0.3~VDD+0.3 -30~+85 -55~+125
Unit
V V V V C C
Note
*1 *4 *1,2 *3,4 -
*1. Based on VSS=0 V *2. Applies to input terminals and I/O terminals at high impedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R)) *3. Applies to V0L(R), V1L(R), V4L(R) and V5L(R). *4. Voltage level: VDD V0L= V0R V1L= V1R V4L= V4R V5L= V5R VEE.
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD=+5V 10%, VSS=0V, |VDD-VEE |=8~17V, T a= -30 ~ +85C) Characteristic Symbol condition Min Typ
Input High Voltage Low Output High Voltage Low Input Leakage Current OSC Frequency On Resistance (Vdiv-Ci) Operating Current VIH VIL VOH VOL ILKG fOSC RON IOH=-0.4 mA IOL=0.4 mA VIN=VDD~VSS Rf=47 k 2% Cf=20pf 5% VDD-VEE =17V Load current = 150A Master mode 1/128 Duty Slave mode 1/128 Duty Master mode 1/128 Duty Master mode External clock Slave mode 0.7VDD VSS VDD-0.4 -1.0 315 450 -
Max
VDD 0.3VDD 0.4 1.0 585 1.5
Unit
V V A KHz k
Note
*1 *2 *1
IDD1 IDD2
50 0.5
-
1.0 200 100 600 1500
mA A
*3 *4 *5
Supply Current Operating Frequency
IEE fop1 fop2
KHz
*1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M and CL2 in the input state. *2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M and CL2 in the output state. *3. This value is specified at about the current flowing through VSS. Internal oscillation circuit: Rf=47 k, Cf=20 pF Each terminal of DS1, DS2, FS, SHL and MS is connected to VDD and out is no load. *4. This value is specified at about the current flowing through VSS. Each terminal of DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD, and MS is connected to VSS. CL2, M, DIO1 is external clock. *5. This value is specified at about the current flowing through VEE. Don't connect to VLCD (V1~V5).
11/20
KS0107B
AC Characteristics (VDD=5V 10%, Ta=-30C~+85C)
1. Master mode (MS=VDD, PCLK2=VDD, Cf=20 pF, Rf=47 k)
CL2
0.7VDD 0 . 3 VD D
64CH COMMON DRIVER FOR DOT MATRIX LCD
tW L C tW H C tS U tD H ts u tW H C tD
D I O 1 ( S H L = VDD ) D I O 2 ( S H L = VSS
)
D I O 2 ( S H L = VDD ) D I O 1 ( S H L = VSS
)
tD tD F
FRM tD M tD M M tF tR tW H 1 0.7VDD 0 . 3 VD D
CLK1
tW L 1
tD I 2 tD 2 1
CLK2 tW H 2
tF
tR
Characteristic Data Setup Time Data Hold Time Data Delay Time FRM Delay Time M Delay Time CL2 Low Level Width CL2 High Level Width CLK1 Low Level Width CLK2 Low Level Width CLK1 High Level Width CLK2 High Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1, CLK2 Rise/Fall Time
Symbol tSU tDH tD tDF tDM tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/tF
Min 20 40 5 -2 -2 35 35 700 700 2100 2100 700 700 -
Typ -
Max 2 2 150
Unit
s
ns
12/20
KS0107B
2. Slave mode (MS=VSS)
64CH COMMON DRIVER FOR DOT MATRIX LCD
tF CL2 ( PLK2 = VSS )
tR
tWLC1 0.7V DD tWHC1 tSU tWHC2 tWLC 0.3V DD
CL2 ( PLK2 = VDD ) tR DIO1 ( SHL = VDD ) DIO2 ( SHL = VSS ) Input Data DIO1 ( SHL = VDD ) DIO2 ( SHL = VSS ) Output Data tH tF tD thcl
0.7VDD 0.3VDD
0.7VDD 0.3V DD
Characteristics CL2 Low Level Width CL2 High Level Width CL2 Low Level Width CL2 High Level Width Data Setup Time Data Hold Time Data Delay Time Output Data Hold Time CL2 Rise/Fall Time *1; Connect load CL=30 pF
Symbol tWLC1 tWHC1 tWLC2 tWHL tSU tDH tD tH tR/tF
Min 450 150 150 450 100 100 10 -
Typ -
Max 200 30
Unit ns ns ns ns ns ns ns ns ns
Note PCLK2=VSS PCLK2=VSS PCLK2=VDD PCLK2=VDD
*1
OUTPUT 30pF
13/20
KS0107B FUNCTIONAL DESCRIPTION
64CH COMMON DRIVER FOR DOT MATRIX LCD
1. RC Oscillator The RC Oscillator generates CL2, M, FRM of the KS0107B, and CLK1 and CLK2 of the KS0108B by the oscillation resister R and capacitor C. When selecting the master/slave mode, the oscillation circuit is as following: 1) Master Mode : in the master mode, use these terminals as shown below.
KS0107B R Rf 47K CR C Cf open 20pF R
KS0107B CR C
open external clock
Internal Oscillation
2) Slave Mode : in the slave mode, stop the oscillator as shown below.
External Clock
KS0107B R CR C
open V DD
open
2. Timing Generation Circuit It generates CL2, M, FRM, CLK1 and CLK2 by the frequency from the oscillation circuit. 1) Selection of Master/Slave (M/S) Mode When M/S is "H", it generates CL2, M, FRM, CLK1 and CLK2 internally. When M/S is "L", it operates by receiving M and CL2 from the master device. 2) Frequency Selection (FS) To adjust FRM frequency by 70 Hz, the oscillation frequency should be as follows: FS H L Oscillation Frequency fOSC=430 kHz fOSC=215 kHz
In the slave mode, it is connected to VDD. 3) Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 L H DS2 L H L H DUTY 1/48 1/64 1/96 1/128
14/20
KS0107B
64CH COMMON DRIVER FOR DOT MATRIX LCD
3. Data Shift & Phase Select Control 1) Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the CL2 according to PCLK2. PCLK2 H L Phase Selection Data shift on rising edge of CL2 Data shift on falling edge of CL2
2) Data Shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS H L SHL H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input Direction of Data C1C64 C64C1 DIO1C1C64DIO2 DIO2C64C1DIO1
15/20
KS0107B TIMING DIAGRAM
1. 1/48 Duty Timing (Master Mode)
Condition: DS1=L, DS2=L, SHL=H(L), PCLK2=H
64CH COMMON DRIVER FOR DOT MATRIX LCD
C CLK1 1 CLK2 2 3 63 64
CL2 FRM DIO1 ( DIO2 ) M C1 ( C48 ) V1 C2 ( C47 ) V1
1
2
3
46
47
48
1
2
3
46
47
48
V0 V4 V4 V0 V4 V1 V0 V1 V5 V5
V1 V1
V0
V4
C47 ( C2 ) V5 C48 ( C1 ) V1 DIO2 ( DIO1 ) - relation of CL2 & V5
V4 V4
V4
V1 V5 V1
V1
V4 V4
V0
V5
DIO1 ( DIO2 )
CLK2 CL2
DIO1 ( DIO2 )
16/20
KS0107B
2. 1/128 duty timing (Master mode)
Condition: DS1=H, DS2=H, SHL=H(L), PCLK2=H
64CH COMMON DRIVER FOR DOT MATRIX LCD
C CLK1 1 CLK2 2 3 23 24
CL2 FRM DIO1 ( DIO2 ) M C1 ( C48 ) V1 C2 ( C47 ) V1
1
2
3
126
127
128
1
2
3
126
127
128
V0 V4 V4 V0 V4 V1 V0 V1 V5 V5
V1 V1
V0
V4
C47 ( C2 ) V5 C48 ( C1 ) V1 DIO2 ( DIO1 ) V5
V4 V4
V4
V1 V5 V1
V1
V4 V4
V0
V5
- relation of CL2 CLK2 CL2
&
DIO1 ( DIO2 )
DIO1 ( DIO2 )
17/20
KS0107B
3. 1/48 Duty Timing (Slave Mode)
Condition: PCLK2=L, SHL=H(L)
64CH COMMON DRIVER FOR DOT MATRIX LCD
1 CL2
2
46
47
48
1
2
46
47
48
~ ~
~ ~ ~ ~
M
~ ~
DIO1 ( DIO2 )
~ ~
~ ~
C1 ( C48 )
V1
V0
V1
V0
~ ~
V4
~
V5
C2 ( C47 )
V1 V4
V0
V1
~ ~
V4
V1 V5
V4
~ ~
V0 V1 C47 ( C2 ) V4 V4 V1 V1
~ ~
V4 V5 V0 V4 V1
~ ~ ~
V4
~ ~
C48 ( C1 )
V5
V5
DIO2 ( DIO1 )
~ ~
~
18/20
KS0107B
4. Power Driver Circuit
VDD
64CH COMMON DRIVER FOR DOT MATRIX LCD
V0 V0L/R R1 V1 V1L/R R1 V2
VDD
KS0107B
R2 V3 R1 V4 V4L/R R1 V5 V5L/R VR VEE To KS0108B
VEE
Relation of duty & bias DUTY 1/48 1/64 1/96 1/128 BIAS 1/8 1/9 1/11 1/12 Rdiv R2=4R1 R2=5R1 R2=7R1 R2=8R1
*When duty factor is 1/48, the value of R1 & R2 should satisfy. R1/(4R1+R2)=1/8 R1=3 K, R2=12 K
19/20
KS0107B
VDD 15
5
15
E
RS
E
R/W
CS3
CS1B
CS2B
RSTB
RS V0R/L FRM M V3R/L V5R/L VEE CLK1 CLK2 CL VSS S1~S64 V2R/L V2R/L V3R/L V5R/L V EE VDD V0R/L S1~S64
R/W
CS3
CS1B
CS2B
RSTB
VDD FRM M CLK1 CLK2 CL Rf Cf VSS
APPLICATION CIRCUIT
1/128 Duty Segment Drive(KS0108B)
KS0108B DB0 ~ DB7
KS0108B DB0 ~ DB7
R
C
FS C1 COM1 SEG1 C64 KS0107B (Master)
CR
MS
VDD SHL
DS2
DS1
PCLK2
SEG128
V SS V OR/L V IR/L V4R/L V5R/L V EE CL2 COM128 open open S1~S64 FRM C64 PCLK2 FS DS1 DS2 SHL RS CL VDD VSS CLK2 R/W CLK1 M VEE V0R/L V2R/L V3R/L V5R/L CS3 CS1B CS2B FRM M CLK1 CLK2 R/W RS M CLK2 DIO2 CLK1 DIO1 2 M CL2 DIO1 DIO2 C1 FRM
Interface Circuit
LCD PANEL
64CH COMMON DRIVER FOR DOT MATRIX LCD
20/20
5 VDD VOR/L VIR/L V4R/L V5R/L VEE VSS MS C 5 open VDD RS R/W V0 V5 VEE MPU V1 V2 V3 V4 E RSTB DB0 - DB7 CS1B CS2B CS3 15 open open open open 15 FRM CR R CLK2 CLK1 RSTB KS0108B E KS0107B (Slave) DB0 ~ DB7
S1~S64
VEE V0R/L V2R/L V3R/L V5R/L CS3 CS1B CS2B DB0 ~ DB7 RSTB E KS0108B
CL VDD V SS
15

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